1. Field of the Invention
The present invention relates to a pulse output circuit, a shift register and a display device.
2. Description of the Related Art
In recent years, a display device in which a circuit is formed on an insulating substrate, specifically on a glass or plastic substrate, by using thin film transistors (hereinafter referred to as TFTs) formed of a semiconductor thin film has been developed. Specifically, development of an active matrix display device has been remarkably advanced. The active matrix display device formed of TFTs includes hundred thousands to millions of pixels which are arranged in matrix, and the TFTs provided in each pixel control the charge of each pixel to display an image.
Further, polysilicon TFTs which have excellence in electrical properties have been developed instead of amorphous TFTs. By using the polysilicon TFFs, a method of forming a driver circuit in the periphery of a pixel portion simultaneously with a pixel TFT constituting a pixel has been developed as a recent technology. The method makes a significant contribution to reduction in size, weight and power consumption of the device, therefore, it is becoming an essential technology for forming the display portion of a portable information terminal or the like whose application fields are remarkably expanding in recent years.
In general, a CMOS circuit which is formed with the combination of an N-type TFT and a P-type TFT is used for a circuit constituting a driver circuit of the display device. The CMOS circuit is characterized in that there is a current flow only when the logic is inverted (from High level to Low level or from Low level to High level), and ideally, there is no current flow while retaining certain data (practically, there is a small amount of leak current flow). Therefore, the CMOS circuit has the advantage of being cable of reducing power consumption considerably in the whole circuit and of operating at high speed because the P-type TFT and the N-type TFT complement each other
However, as for the manufacturing step of the CMOS circuit, the number of steps is increased due to the complicated steps of ion doping or the like, and thus, it is difficult to reduce the production cost. Consequently, a circuit which is formed of TFTs of a single conductivity type, that is, either of N-type TFTs or P-type TFTs, and is capable of operating at as high speed as a CMOS circuit has been proposed instead of a conventional circuit formed of a CMOS circuit (see Patent Document 1, for example).
According to a circuit disclosed in Patent Document 1, as shown in FIGS. 2A to 2C, a gate electrode of a TFT 205 connected to an output terminal is made temporarily in a floating state, and by using capacitive coupling between a gate and source of the TFT 205, the potential of the gate electrode can be made higher than a power source potential. As a result, an output without amplitude attenuation can be obtained without causing a voltage drop due to a threshold voltage of the TFT 205.
Such operation in the TFT 205 is known as a bootstrap operation. This operation facilitates the output of pulse without causing a voltage drop due to a threshold voltage of the
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-335153
With reference to a pulse output circuit shown in FIG. 2B, a potential of an output node is focused. FIG. 2C shows operation timing of a shift register shown in FIG. 2A. During a period in which no pulse is inputted and outputted, potentials of input terminals 2 and 3 in the pulse output circuit shown in FIG. 2B are Low level, that is, TFTs 201 to 204 are all turned OFF. As a result, gate electrodes of the TFT 205 and a TFT 206 both become in a floating state.
At this time, either a clock signal CK 1 or a clock signal CK 2 is inputted to an input terminal 1, namely a drain region of the TFT 205 which corresponds to a first electrode of the TFT 205 (as to source and drain regions of the TFT 205, a lower potential part is referred to as a source region and a higher potential part is referred to as a drain region herein). Due to a capacitive coupling with the drain region, the potential of the gate electrode of the TFT 205 which is in a floating state, namely a potential of a node α is varied as noise in accordance with a clock signal as shown in FIG. 2C with a reference numeral 250.
This variation in potential is much smaller as compared with pulses with normal amplitude, therefore, it is not so serious when a power source voltage (potential difference between VDD and VSS) is sufficiently large. That is, there is few possibility of the malfunction of the TFT 205 caused by the variation in potential such as noise. However, the TFT 205 is likely to malfunction in the case of adopting a low voltage operation to reduce power consumption or the like.
In view of the foregoing, it is the primary object of the invention to provide a pulse output circuit and a shift register which are capable of reducing the noise in a circuit and operating more accurately.